1. Field of the Invention
The present invention relates to a method for producing a circuit structure. More particularly, the present invention is concerned with a method for producing a circuit structure having an insulator layer comprising a porous silicon oxide thin film, which comprises (1) forming a preliminary insulator layer comprising a silicon oxide-organic polymer composite thin film formed on a substrate, which silicon oxide-organic polymer composite thin film comprises a silicon oxide having an organic polymer dispersed therein, (2) forming, in the preliminary insulator layer, a groove which defines a pattern for a circuit, (3) forming, in the groove, a metal layer which functions as a circuit, and (4) removing the organic polymer from the preliminary insulator layer to render the preliminary insulator layer porous, thereby converting the preliminary insulator layer to an insulator layer comprising a porous silicon oxide thin film. By the method of the present invention, not only can the line-to-line capacitance in the circuit structure be lowered, but also a low resistance metal, such as copper or silver, can be used as a material for a circuit, so that it has become possible to produce an excellent circuit structure in which the delay in the transmission of the electric signal (this phenomenon is the so-called xe2x80x9cinterconnect delayxe2x80x9d) is greatly suppressed, as compared to the case of the conventional circuit structures. Further, by the method of the present invention, it has become possible to produce such an excellent circuit structure with high efficiency.
The present invention is also concerned with a multilayer circuit board comprising the above-mentioned excellent circuit structure, and a semiconductor device comprising the above-mentioned excellent circuit structure.
2. Prior Art
Conventionally, as a material for an insulator layer used in a multilayer circuit of a semiconductor device, such as an LSI, a non-porous silicon oxide or a silicon oxide having incorporated therein a fluorine atom or an organic group has been used. However, the dielectric constants of such materials are high. In recent years, the density of the circuit in a semiconductor device, such as an LSI, has been increasing and, hence, the distance between the adjacent conductive paths of the circuit has been decreasing. Due to the decreased distance between the adjacent conductive paths of the circuit, the adjacent conductive paths function as a capacitor. In this case, when the dielectric constant of the insulator layer is high, a problem arises that the capacitance in the circuit becomes large, thereby leading to the delay in the transmittance of the electric signal through the circuit (i.e., interconnect delay). Therefore, in order to lower the dielectric constant of the insulator layer, it is attempted to use an insulator layer composed of a composite of a silicon oxide and an organic polymer, or a porous silicon oxide, i.e., a composite of a silicon oxide and air which has a dielectric constant of approximately 1.
In the future, when the density of the circuit of a semiconductor device, such as an LSI, has further increased, the importance of the alleviation of the interconnect delay would become much greater than that at present. Therefore, in addition to the lowering of the dielectric constant of the insulator layer, it also becomes necessary to use, as a material for a circuit, a low resistance metal represented by copper and silver instead of the conventionally used aluminum. However, in the conventional process for producing a circuit structure, it is difficult to use such a low resistance metal as a material for a circuit. The reason is as follows. The conventional process comprises: forming a metal layer on the entire surface of a substrate; forming, on the metal layer, a photoresist pattern (protective layer), which corresponds to the desired circuit pattern; removing the non-protected portions of the metal layer (i.e., the portions of the metal layer which are not covered by the photoresist pattern) by the conventional etching process, thereby forming a circuit on the substrate; and coating the circuit with an insulator layer. The above-mentioned conventional etching process utilizes a substance which is capable of forming a high vapor pressure compound with the metal used for forming the circuit. In such a conventional etching process, the protected portions of the metal layer, which are covered by the photoresist, are not eroded, and only the non-protected portions of the metal layer are converted into a high vapor pressure substance, so that the non-protected portions of the metal layer are selectively removed. However, when the metal layer is formed from a low resistance metal represented by copper and silver, such a low resistance metal cannot form a high vapor pressure compound, but forms only a low vapor pressure compound, so that the circuit cannot be formed by the conventional etching process. Therefore, in the conventional techniques, the above-mentioned low resistance metal cannot be used as a material for forming a circuit.
In order to solve the above-mentioned problems, the so-called xe2x80x9cdamascene processxe2x80x9d has been proposed. The damascene process comprises: forming an insulator layer on a substrate; forming, in the insulator layer, a groove which defines a pattern for a circuit; forming a layer of a metal on the entire surface of the insulator layer, so that the groove is completely filled with the metal; removing the metal which is not present in the groove by etch back method utilizing a plasma or chemical mechanical polishing (CMP) method, so that the surfaces of the insulator layer and the surface of the metal layer (which functions as a circuit) are exposed (with respect to the damascene method, reference can be made to, for example, xe2x80x9cInternational Electron Device Meeting Technical Digestxe2x80x9d (1997), p. 773-776, and Unexamined Japanese Patent Application Laid-Open Specification No. 62-102543). Thus, in the damascene process, the formation of the circuit need not be conducted by the conventional etching method, but can be conducted by etch back method utilizing a plasma or chemical mechanical polishing (CMP) method. Therefore, in the damascene process, a low resistance metal, such as copper or silver, can be used as a material for the circuit.
Further, as well known in the art, when the damascene process is employed for the production of a multilayer circuit board comprising a laminate of a plurality of circuit structures, the number of steps required for the production is small, as compared to that in the conventional process. Therefore, the damascene process is very advantageous for reducing the production cost.
Specifically, in the production of a multilayer circuit board by a conventional method, the formation of a new (upper) circuit structure on a (lower) circuit structure which has been already formed is conducted by a process comprising the steps of: forming, on the lower circuit structure, an insulator layer for separating the lower circuit structure from the upper circuit structure to be formed; forming, in the insulator layer, a vertical through-hole for accommodating therein a vertical conductive path which electrically connects the lower circuit structure and the upper circuit structure to be formed; forming a vertical conductive path in the through-hole; and forming the upper circuit structure in the same manner as mentioned above in connection with the conventional process for producing a circuit structure.
By contrast, in the damascene process, after an insulator layer for separating the lower circuit structure from the upper circuit structure (to be formed) is formed on the lower circuit structure, the formation of the vertical through-hole for accommodating therein a vertical conductive path (which electrically connects the lower circuit structure and the upper circuit structure to be formed) and the formation (in the insulator layer separating the lower circuit structure from the upper circuit structure) of the groove which defines a pattern for a circuit of the upper circuit structure can be conducted in a single step. Then, the above-mentioned vertical through-hole and the above-mentioned groove can be simultaneously filled with the metal. After the vertical through-hole and the groove are filled with the metal, the upper circuit structure can be completed by only removing the metal which is not present in the groove by the above-mentioned etch back method utilizing a plasma or the above-mentioned chemical mechanical polishing (CMP) method. Thus, the damascene process is very advantageous not only in that a low resistance metal, such as copper or silver, can be used, but also in that the number of steps required for the production of a multilayer circuit board is small, as compared to that in the conventional process.
However, the conventional damascene process has the following problem. The insulator layer used in the conventional damascene process is composed of a silicon oxide and is produced by plasma chemical vapor deposition (CVD). This silicon oxide insulator layer has a high dielectric constant and, hence, the interconnect delay cannot be satisfactorily suppressed. In order to solve this problem, it has been proposed to employ an insulator layer having a dielectric constant lower than that of the above-mentioned silicon oxide insulator layer produced by plasma CVD.
For example, it is known to use an insulator layer composed of a composite of a silicon oxide and an organic polymer. With respect to the above-mentioned organic polymer used in such an insulator layer, the organic polymer needs to have a low dielectric constant so as to obtain an insulator layer having a satisfactorily low dielectric constant. Examples of such organic polymers include paraquinoxaline (dielectric constant: 2.70) reported by Hedrick et al (Polymer, Vol. 34, p. 4717 (1993)) and polyquinoline (dielectric constant: 2.5) reported by Monk et al (Polymers for Dielectric and Photonic Applications, p. 119, (1993)).
However, the above-mentioned silicon oxide-organic polymer composite cannot be used for producing an insulator layer having a satisfactorily low dielectric constant.
In this situation, a technique employing a porous silicon oxide film as the insulator layer has been drawing attention. In this technique, the dielectric constant of a silicon oxide film is lowered by rendering the silicon oxide film porous to thereby obtain a composite of the silicon oxide and air. This technique is described in, for example, U.S. Pat. No. 5,472,913. Specifically, with respect to the insulator layer, this patent document describes the use of a porous silicon oxide film produced by a method comprising: subjecting a tetralkoxysilane to hydrolysis and dehydration condensation in an alcohol to form a wet silicon oxide gel film; and immersing the formed wet silicon oxide gel film in a solution of trimethylchlorosilane (which is a silylation agent) to thereby render water repellent the surface of the wet silicon oxide gel film, followed by drying under atmospheric pressure. However, it has conventionally been very difficult to produce a circuit structure having a insulator layer composed of a porous silicon oxide by the damascene process, for the following reason.
In the above-mentioned U.S. Pat. No. 5,472,913, the porous silicon oxide film obtained by the above-mentioned method is covered with a protective layer composed of a non-porous silicon oxide. Then, the protective layer is etched by lithography method, followed by the formation of the above-mentioned vertical through-hole by etching the porous silicon oxide film (insulator layer) under conditions different from those employed in the etching of the protective layer. However, even when the thickness of the protective layer composed of the non-porous silicon oxide is only slightly uneven, the porous silicon oxide (positioned below the protective layer) is caused to be unevenly etched at a speed several times higher than that in the case of the etching of the protective layer. Therefore, the thickness of the protective layer and the etching conditions must be strictly controlled, thereby causing a great difficulty.
Thus, generally, when it is attempted to process finely the porous silicon oxide film so as to form a circuit on the porous silicon oxide film, a great difficulty is encountered due to the poor resistance of the porous silicon oxide against the dry etching and the like.
Further, the damascene process has the following problem. In the damascene process, a metal layer is formed on the insulator layer having a fine groove which defines the pattern for a circuit. Therefore, when the porous silicon oxide film is used as the insulator layer, there is a danger that the metal intrudes into the pores of the insulator layer during the formation of the metal layer. This problem also renders difficult the use of the porous silicon oxide film in the damascene process.
Further, in the damascene process, it is necessary to employ an etch back method or a chemical mechanical polishing (CMP) method for removing the metal which is not present in the groove or removing a part of the insulator layer (for forming a vertical through-hole). However, when the porous silicon oxide film is used as the insulator layer, disadvantages are likely to be caused during the etch back or the CMP. Specifically, in the case of the etch back method utilizing a plasma, when the porous silicon oxide is exposed to the plasma, the gas generated during the etching is trapped in the pores of the insulator layer, or the insulator layer is damaged. Further, in the case of the CMP, since an acidic or alkaline aqueous slurry containing abrasive particles is used, there is a danger that the insulator layer is dissolved or damaged.
In order to solve the above-mentioned problems, Zielinski et al propose a method in which, prior to the formation of the metal layer and the subsequent CMP, the porous silicon oxide film having a groove (which defines the pattern for a circuit) is covered with a protective layer composed of a non-porous silicon oxide film (International Electron Device Meeting Technical Digest (1997) p. 936-938). In this method, the abrasion of the porous silicon oxide film can be prevented by the protective layer. Therefore, this method is free from the above-mentioned problem of the damage to the porous silicon oxide film. Further, since the side walls of the groove are also protected by the nonporous silicon oxide film, the danger of the intrusion of the metal into the pores of the insulator layer can be alleviated.
However, this method has a problem that the step of formation of the protective layer is necessary, so that the process for forming the circuit structure becomes cumbersome. In addition, this method has a problem that the non-porous silicon oxide film (having a high dielectric constant) remains on a part of the surface of the insulator layer and the side walls of the groove, so that, despite that the porous silicon oxide film is used as the insulator layer, a satisfactorily low dielectric constant cannot be achieved.
In this situation, the present inventors have made extensive and intensive studies toward solving the above-mentioned problems accompanying the prior art and developing a method for efficiently producing a circuit structure having an insulator layer comprising a porous silicon oxide film which has a high dielectric constant by the commercially advantageous damascene process. As a result, it has unexpectedly been found that this object can be attained by a method comprising: (1) forming a preliminary insulator layer comprising a silicon oxide-organic polymer composite thin film formed on a substrate, which silicon oxide-organic polymer composite thin film comprises a silicon oxide having an organic polymer dispersed therein, (2) forming, in the preliminary insulator layer, a groove which defines a pattern for a circuit, (3) forming, in the groove, a metal layer which functions as a circuit, and (4) removing the organic polymer from the preliminary insulator layer to render the preliminary insulator layer porous, thereby converting the preliminary insulator layer to an insulator layer comprising a porous silicon oxide thin film. The present invention has been completed, based on this novel finding.
Accordingly, it is a primary object of the present invention to provide a method based on the damascene process, which can be used for easily and efficiently producing a circuit structure in which the capacitance between the adjacent conductive paths of the circuit (i.e., line-to-line capacitance) is small, so that the delay in the transmittance of the electric signal through the circuit (i.e., interconnect delay) is small, wherein the damascene process is commercially advantageous not only in that a low resistance metal, such as copper or silver, can be used as a material for a circuit, but also in that this process is suitable for the production of a multilayer circuit board.
Another object of the present invention is to provide a multilayer circuit board and a semiconductor device, each comprising the above-mentioned excellent circuit structure.
The foregoing and other objects, features and advantages of the present invention will be apparent from the following detailed description and claims taken in connection with the accompanying drawings.